Interconnects have been, are, and will continue to be a limiting factor for the performance and cost of integrated circuits. As technology scales down further, the problems associated with interconnects become ever more pressing. The introduction of low-resistive copper as an alternative interconnect material for aluminum presents researchers with some new challenges, since copper cannot be implemented in the same manner as aluminum alloys.
As feature sizes shrink, narrower copper trenches need to be formed. Also to facilitate closer packing and multilevel connections, trenches are getting proportionally smaller as they get narrower. These deep trenches etched into the dielectric must be filled completely, without voids or defects.
Physical Vapor Deposition (PVD) has long time been one of the techniques of choice for metallization in integrated circuits. In particular, sputter deposition has been widely used in the manufacturing of high-performance on-chip interconnect. However, due to the limitations of the PVD techniques and the continuing feature sizes it is generally believed that the applicability of PVD for the filling of deep trenches is coming to an end. Sputtering techniques are however widely used to deposit a thin layer of diffusion barrier and/or seed layer in said features. Unfortunately, PVD suffers from shadowing effects if the aspect ratio of features to be filled is sufficiently large. Said shadowing effects can form overhanging structures at the top corners of the trenches and vias. These effects can lead to void formation when attempting to fill a feature. Due to the geometrical shadowing, the film is preferentially deposited on the top corners leading to a “void” within the trench or via.
Electroplated (also referred to as electrochemically deposited or ECD) copper has therefore become the method of choice for filling narrow interconnect features in the back-end-of-line processing for microelectronics applications. However, as the trench width decreases, the influence of the PVD deposited seed layer becomes more important when its thickness is not scaled accordingly. This changes the grain growth dynamics in trenches as the volume fractions of ECD and PVD change significantly.
Typically copper lines are fabricated by patterning trenches into a dielectric layer with optical lithography. A barrier layer and Cu seed are deposited within the trenches, followed by electroplating in order to fill the structures. A Chemical mechanical polishing (CMP) step is used to remove excess copper and barrier material. A standard hot-plate anneal step (e.g. 30′ at 250° C.) is introduced before CMP to enhance re-crystallization of copper in both seedlayer and plated copper.
The grain growth mechanism in thin PVD copper seed films and in plated (ECD) copper has been described by many authors. Typically, two growth modes are seen to occur simultaneously, known as normal and secondary grain growth to those working in the field. The latter leads to grain sizes of several times the thickness of a thin film or width of a trench and grain boundary motion is erratic. Normally grain growth in the seedlayer is intently retarded through process conditions in order to create a stable film for the subsequent ECD process.
Recently, a novel highly concentric grain growth mode, different from the commonly observed secondary grain growth (SGG) in ECD copper as described above, referred to as super-secondary-grain-growth (SSGG) has been discovered in thick PVD copper films by Vanstreels et al. Said SSGG was shown to occur only on alpha-Ta and produce copper grains of many tens of micrometers. In a second stage the SSGG grains initiated in the thick Physical Vapor Deposited (PVD) copper on alpha-Ta were shown to also be able to recrystallize a bilayer of said layer and an ECD Cu layer. In both the ‘PVD-only’ and the ‘PVD-ECD bilayers’ on alpha-Ta, the SSGG and SGG are both active and their rivalry determines the final grain structure obtained. It was shown by Vanstreels et al that SSGG dominates at low temperature, but that SGG gains in importance when the temperature is increased.
Because the SSGG produces [100] oriented super grains of several tens of micrometers, less grain boundaries are obtained and hence the resistance in copper having these super grains is lower. This makes the application of SSGG in interconnect structures very attractive. There is however still a need to understand the growth mechanisms of said SSGG, and to have said SSGG lead to large grains in interconnect structures (e.g. trenches) in semiconductor devices. So far, only growth in thin films has been demonstrated because the required thickness needed to make SSGG possible is larger than typical trench dimensions.